1. Field of the Invention
The present invention pertains generally to electrical computers and more particularly to systems and methods of generating data for testing an electrical circuit.
2. Description of Related Art
Microelectronic integrated circuits (ICs), such as computer chips, are used in a variety of products including personal computers, automobiles, communication systems, and consumer electronics products. To produce an IC, a manufacturer must first design an electronic circuit to integrate (i.e., manufacture) into a chip. This stage of the design process typically requires a designer to simulate a circuit description in a circuit simulator and compare the simulated results with expected results to verify the proper operation of the circuit design. A circuit design representation, such as a circuit netlist or a Register Transfer Level (RTL) description, is input into the simulator to provide a description of the circuit to be simulated. A netlist is typically a list of electronic logic cells with a description of the connections between the inputs and the outputs of the various logic cells. An RTL description is a description of the functionality of the circuit, much like programming source code is a description of the functionality of a software program.
To simulate the circuit, the designer must also provide input stimulus to the simulation. Input stimulus represents a set of input signals required to drive specific functional aspects of the circuit during simulation. Generally, the input stimulus used in circuit simulation is created by the designer to simulate and verify the operation of the circuit design embodied in the design representation. The input stimulus is primarily based on anticipated real world conditions (e.g., the conditions of an IC found in a cellular phone) and on requirements for properly exercising particular functional blocks within the circuit.
After a circuit is designed, it is manufactured into an IC by way of a microelectronics fabrication process. Fabrication involves multiple stages of chemical processing to create a physical IC having, for example, solid state transistors, solid state resistors, input/output pads, metal interconnections and so on. Various design, manufacturing, and operational conditions can cause a manufactured IC to perform incorrectly after it has been fabricated. Therefore, an IC manufacturer typically tests the operation of every IC it produces to verify proper operation.
The testing of an IC requires high speed testers, typically called Automated Test Equipment (ATE) systems, that can test hundreds of chips per hour. Like circuit simulators, ATE systems also require input and output information (called "test patterns") to drive the IC and to verify results during testing. However, in contrast to simulators, the high speed requirements and hardware limitations of an ATE system restrict the timings and waveforms of the test patterns. As such, the "real world" timings and waveforms of the simulation's input stimulus cannot always be reproduced on an ATE system. For example, a simulator's input signal may transition from a logical `0` to a logical `1` at a non-integer number of nanoseconds, but on a particular ATE system, input signal transactions may be limited to 5 nanosecond increments. These testing restrictions can also vary depending on the particular ATE system that is to be used during the test. Accordingly, the designer must provide tester-compatible test pattern timings for each input signal so that the test patterns comply with the target ATE system's limitations. Input stimulus and test patterns in which every input signal conforms to the target ATE system's restrictions are termed "tester-compatible," whereas input stimulus and test patterns that do not conform are termed "non-tester-compatible". Generation of test patterns from non-tester-compatible simulation output requires modification of input signal timing to become tester-compatible, but such modifications can introduce changes in the simulated circuit operation or results. In contrast, it is desirable to generate test patterns that are compatible with a particular ATE system and that may be generated from the output of a simulation executed with tester-compatible input stimulus. In this manner, both the simulator input stimulus and the ATE test patterns would be tester compatible, thereby verifying the same circuit operation and results.
Therefore, IC design engineers need a method of generating tester-compatible input stimulus and test patterns from non-tester compatible input stimulus so that the physical device tests on the ATE system are substantially equivalent to the simulated conditions. Furthermore, a translation from non-tester-compatible to tester-compatible may introduce or require changes in the circuit operation or results; therefore, a need exists to conveniently re-simulate the translated input stimulus, so as to obtain simulations and physical tests that verify the same functionality and achieve the same results.